EPM9320ALC84-10 vs EPM9320ARC208-10 Vergleich
Detaillierter Direktvergleich von EPM9320ALC84-10 von Intel und EPM9320ARC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
EPM9320ARC208-10 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9320ALC84-10 | EPM9320ARC208-10 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,80 | $21,40 |
| Family | MAX 9000 | — |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 52 | — |
| Dedicated Inputs | 16 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Supply Voltage (VCCINT) | 5.0 V | — |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM-based, third-generation MAX | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) | — |
| Gehäuse | 84-pin PLCC (J-Lead) | RQFP-208 (Power Quad Flat Pack) |
| Betriebstemperatur | [DATA_NEEDED: commercial/industrial grade] | [DATA_NEEDED: operating temperature range] |
| Montageart | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| RoHS-Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance status] |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) | — |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect | — |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Maximum Frequency | — | 144.9 MHz |
| Versorgungsspannung | — | 5.0 V |
| Logic Blocks (LABs) | — | 16 |
| Programmability | — | EEPROM, in-system programmable via JTAG |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |