EPM9320ALC84-10 vs EPM9320ARC208-10 Comparaison
Comparaison détaillée côte à côte de EPM9320ALC84-10 par Intel et EPM9320ARC208-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9320ALC84-10 | EPM9320ARC208-10 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,80 | $21,40 |
| Family | MAX 9000 | — |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 52 | — |
| Dedicated Inputs | 16 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Supply Voltage (VCCINT) | 5.0 V | — |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM-based, third-generation MAX | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) | — |
| Boîtier | 84-pin PLCC (J-Lead) | RQFP-208 (Power Quad Flat Pack) |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial grade] | [DATA_NEEDED: operating temperature range] |
| Type de montage | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| Statut RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance status] |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) | — |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect | — |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Maximum Frequency | — | 144.9 MHz |
| Tension d'alimentation | — | 5.0 V |
| Logic Blocks (LABs) | — | 16 |
| Programmability | — | EEPROM, in-system programmable via JTAG |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |