EPM9320ALC84-15 vs EPM9320ALC84-10 Vergleich

Detaillierter Direktvergleich von EPM9320ALC84-15 von Altera und EPM9320ALC84-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320ALC84-15 EPM9320ALC84-10
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $19,80
Family MAX 9000 CPLD MAX 9000
Macrocells 320 320
Usable Gates 6000 —
Propagation Delay (tPD) 16 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
User I/O 56 —
Logic Array Blocks (LABs) 16 16
Technology CMOS, EEPROM-based configuration CMOS EEPROM-based, third-generation MAX
Gehäuse 84-pin PLCC (S-PQCC-J84, J-lead) 84-pin PLCC (J-Lead)
Montageart Through-hole / socket Surface Mount / Through-Hole (PLCC socket)
Programming Interface JTAG (IEEE 1149.1) / ISP —
Betriebstemperatur -40C to +85C (industrial) [DATA_NEEDED: commercial/industrial grade]
RoHS-Status [DATA_NEEDED: rohs status] [DATA_NEEDED]
Feuchtigkeitsempfindlichkeitsgrad (MSL) MSL-3 (168 hours per fpgalink.com) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead free status] —
RoHS3 Compliance ROHS3 Compliant (per fpgalink.com listing) —
Device — EPM9320
Maximum User I/O Pins — 52
Dedicated Inputs — 16
Speed Grade — -10 (10 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) — 10 ns
Supply Voltage (VCCINT) — 5.0 V
In-System Programmability — 5.0 V ISP via IEEE 1149.1 JTAG
PCI Compliance — PCI Local Bus Specification Rev. 2.2 (speed grade -10)
Non-Volatile Configuration — Yes (EEPROM cell, powers up in known state)
Architecture — MAX (Multiple Array MatriX) with FastTrack Interconnect

Datenblätter & Ressourcen

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