EPM9320ALC84-15 vs EPM9320ALC84-10 对比

详细并排对比 EPM9320ALC84-15 出自 Altera 和 EPM9320ALC84-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320ALC84-15 EPM9320ALC84-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $9.95 $19.80
Family MAX 9000 CPLD MAX 9000
Macrocells 320 320
Usable Gates 6000 —
Propagation Delay (tPD) 16 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
User I/O 56 —
Logic Array Blocks (LABs) 16 16
Technology CMOS, EEPROM-based configuration CMOS EEPROM-based, third-generation MAX
封装 84-pin PLCC (S-PQCC-J84, J-lead) 84-pin PLCC (J-Lead)
安装类型 Through-hole / socket Surface Mount / Through-Hole (PLCC socket)
Programming Interface JTAG (IEEE 1149.1) / ISP —
工作温度 -40C to +85C (industrial) [DATA_NEEDED: commercial/industrial grade]
RoHS 状态 [DATA_NEEDED: rohs status] [DATA_NEEDED]
湿敏等级(MSL) MSL-3 (168 hours per fpgalink.com) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead free status] —
RoHS3 Compliance ROHS3 Compliant (per fpgalink.com listing) —
Device — EPM9320
Maximum User I/O Pins — 52
Dedicated Inputs — 16
Speed Grade — -10 (10 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) — 10 ns
Supply Voltage (VCCINT) — 5.0 V
In-System Programmability — 5.0 V ISP via IEEE 1149.1 JTAG
PCI Compliance — PCI Local Bus Specification Rev. 2.2 (speed grade -10)
Non-Volatile Configuration — Yes (EEPROM cell, powers up in known state)
Architecture — MAX (Multiple Array MatriX) with FastTrack Interconnect

数据手册与资源

浏览全部产品 创建 BOM 获取报价