EPM9320ALC84-20 vs EPM9320LI84-20 Vergleich
Detaillierter Direktvergleich von EPM9320ALC84-20 von Altera und EPM9320LI84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320ALC84-20 | EPM9320LI84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,50 | $12,80 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Gehäuse | PLCC-84 | 84-PLCC (J-Lead, plastic LCC) |
| Process Technology | 0.5 µm CMOS EEPROM | High-performance CMOS EEPROM |
| Versorgungsspannung | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Betriebstemperatur | [DATA_NEEDED: commercial or industrial grade] | -40 C to +85 C (industrial) |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket-compatible) |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| RoHS-Status | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | — | Altera (acquired by Intel) |
| User I/Os | — | 60 |
| Propagation Delay (tPD) | — | 20 ns |
| Internal Frequency | — | 118 MHz |
| Logic Family | — | CMOS, EEPROM-based |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |