EPM9320ARC208-10N vs EPM9320RC208-20N Vergleich
Detaillierter Direktvergleich von EPM9320ARC208-10N von Altera und EPM9320RC208-20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320ARC208-10N | EPM9320RC208-20N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,45 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 320 | 320 |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | 168 |
| Dedicated Input Pins | 12 | — |
| Gehäuse | 208-pin RQFP (BFQFP with exposed pad) | 208-pin RQFP (PowerQuad II) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EEPROM | EEPROM (non-volatile) |
| RoHS-Status | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 |
| Logic Type | — | Complex Programmable Logic Device (CPLD) |
| Usable Gates | — | 6,000 |
| Logic Array Blocks | — | 20 |
| Maximum Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Versorgungsspannung | — | 5.0 V |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL-Level | — | [DATA_NEEDED: MSL level] |