EPM9320ARI208-10N vs EPM9320ARC208-10N Vergleich
Detaillierter Direktvergleich von EPM9320ARI208-10N von Altera und EPM9320ARC208-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM9320ARI208-10N | EPM9320ARC208-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $19,45 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | — |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | 10 ns |
| Versorgungsspannung | 4.5 V to 5.5 V | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | 0C to +70C (Commercial) |
| Gehäuse | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (BFQFP with exposed pad) |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS-Status | unknown | Compliant (lead-free 'N' suffix) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 320 |
| Logic Gates | — | 6,000 gates |
| Maximum Frequency | — | 144.9 MHz |
| Supply Voltage (VCC) | — | 5 V |
| User I/O Pins | — | 168 |
| Dedicated Input Pins | — | 12 |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Configuration Memory | — | Non-volatile EEPROM |