EPM9320ARI208-10N vs EPM9320RI208-10N Vergleich
Detaillierter Direktvergleich von EPM9320ARI208-10N von Altera und EPM9320RI208-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM9320ARI208-10N | EPM9320RI208-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $27,20 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 20 |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Versorgungsspannung | 4.5 V to 5.5 V | 5 V |
| Betriebstemperatur | -40 C to +85 C (industrial) | — |
| Gehäuse | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (PowerQuad II) |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS-Status | unknown | Compliant (N suffix = lead-free) |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 320 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG/ISP) |
| Betriebstemperaturbereich | — | -40C to +85C (industrial) |
| Lead Finish | — | Lead-free (matte tin) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |