EPM9320ARI208-10N vs EPM9320RI208-10N 对比
详细并排对比 EPM9320ARI208-10N 出自 Altera 和 EPM9320RI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N Obsolete规格对比
| 参数 | EPM9320ARI208-10N | EPM9320RI208-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.20 | $27.20 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 20 |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| 电源电压 | 4.5 V to 5.5 V | 5 V |
| 工作温度 | -40 C to +85 C (industrial) | — |
| 封装 | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (PowerQuad II) |
| 安装类型 | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS 状态 | unknown | Compliant (N suffix = lead-free) |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 320 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG/ISP) |
| 工作温度范围 | — | -40C to +85C (industrial) |
| Lead Finish | — | Lead-free (matte tin) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |