EPM9320LC84-15 vs EPM9320GC280-15 Vergleich
Detaillierter Direktvergleich von EPM9320LC84-15 von Intel und EPM9320GC280-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteSpezifikationsvergleich
| Parameter | EPM9320LC84-15 | EPM9320GC280-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,95 | $92,50 |
| Family | MAX 9000 | MAX 9000 (EPM9320) |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Logic Array Blocks (LABs) | 20 | 20 (16 macrocells per LAB) |
| Propagation Delay (tPD) | 15 ns (max) | — |
| Maximale Taktfrequenz | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | 4.75 V to 5.25 V |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Gehäuse | 84-pin PLCC (Plastic Leaded Chip Carrier) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Montageart | Surface Mount | Through-hole (PGA socket) |
| Betriebstemperatur | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to +70 C (commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| RoHS-Status | [DATA_NEEDED: confirm from manufacturer] | ROHS3 compliant (per fpgalink listing) |
| Architecture | — | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Maximum User I/O Pins | — | 164 |
| I/O Voltage Levels | — | 3.3 V or 5 V (configurable) |
| MSL-Level | — | 3 (168 hours) |
| Technology Node | — | CMOS EEPROM, third-generation MAX |