EPM9320LC84-15 vs EPM9320GC280-15 Comparación
Comparación detallada lado a lado de EPM9320LC84-15 por Intel y EPM9320GC280-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteComparación de especificaciones
| Parámetro | EPM9320LC84-15 | EPM9320GC280-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,95 | $92,50 |
| Family | MAX 9000 | MAX 9000 (EPM9320) |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Logic Array Blocks (LABs) | 20 | 20 (16 macrocells per LAB) |
| Propagation Delay (tPD) | 15 ns (max) | — |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | 4.75 V to 5.25 V |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Tipo de montaje | Surface Mount | Through-hole (PGA socket) |
| Temperatura de funcionamiento | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to +70 C (commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Estado RoHS | [DATA_NEEDED: confirm from manufacturer] | ROHS3 compliant (per fpgalink listing) |
| Architecture | — | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Maximum User I/O Pins | — | 164 |
| I/O Voltage Levels | — | 3.3 V or 5 V (configurable) |
| Nivel MSL | — | 3 (168 hours) |
| Technology Node | — | CMOS EEPROM, third-generation MAX |