EPM9320LC84-20N vs EPM9320LC84-10 Vergleich

Detaillierter Direktvergleich von EPM9320LC84-20N von Intel und EPM9320LC84-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320LC84-20N EPM9320LC84-10
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,25 $84,96
Series MAX 9000 —
Logic Family CMOS (EEPROM-based) —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 6,000 6000 (typical)
Macrocells 320 320
User I/Os 60 —
Anzahl der Pins 84 —
Package Type Plastic Leaded Chip Carrier (PLCC-84, J-bend) —
Package Code QCCJ —
Propagation Delay (tPD) 16 ns —
Internal Frequency 118 MHz —
Supply Voltage (VCC) 5 V 5.0 V (typical, see datasheet)
Betriebstemperatur 0 C to +70 C (Commercial) 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix]
Programming 5.0-V In-System Programmable via JTAG (IEEE 1149.1) —
Montageart Surface Mount (J-bend) Surface Mount (PLCC socket also common)
Terminal Form J BEND —
MSL-Level [DATA_NEEDED: MSL moisture sensitivity level] —
RoHS-Status [DATA_NEEDED: RoHS compliance status] ROHS3 Compliant (per fpgalink listing)
Family — MAX 9000 EPLD
Device — EPM9320
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 168 (varies by package)
Pin-to-Pin Logic Delay (tPD) — 10 ns
Maximum Frequency (fCNT) — [DATA_NEEDED: fCNT in MHz]
Process Technology — 0.7 µm CMOS EEPROM/UV-EPROM
Gehäuse — 84-pin PLCC (JEDEC MO-047)
Programming Interface — JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible
Configuration — Non-volatile EEPROM (instant-on, no boot PROM)
Feuchtigkeitsempfindlichkeitsgrad (MSL) — MSL-3, 168 hours (per fpgalink listing)
Manufacturer Lead Time — 1-7 days (per fpgalink listing)

Datenblätter & Ressourcen

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