EPM9320LI84-20N vs EPM9320LC84-15 Vergleich
Detaillierter Direktvergleich von EPM9320LI84-20N von Altera und EPM9320LC84-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LI84-20N | EPM9320LC84-15 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $17,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| Gehäuse | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | 15 ns (max) |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| Versorgungsspannung | 5.0 V | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 20 |
| Maximale Taktfrequenz | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Montageart | — | Surface Mount |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |