EPM9320LI84-20N vs EPM9320LC84-15 对比
详细并排对比 EPM9320LI84-20N 出自 Altera 和 EPM9320LC84-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320LI84-20N | EPM9320LC84-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $17.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| 封装 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | 15 ns (max) |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| 电源电压 | 5.0 V | — |
| 工作温度 | 0 C to +70 C (commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 20 |
| 最大时钟频率 | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| 安装类型 | — | Surface Mount |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |