EPM9320RC208-20N vs EPM9320ARC208-10 Vergleich
Detaillierter Direktvergleich von EPM9320RC208-20N von Altera und EPM9320ARC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
EPM9320ARC208-10 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9320RC208-20N | EPM9320ARC208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $21,40 |
| Device Family | MAX 9000 | MAX 9000 |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks | 20 | — |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Versorgungsspannung | 5.0 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| User I/O Pins | 168 | — |
| Gehäuse | 208-pin RQFP (PowerQuad II) | RQFP-208 (Power Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 144.9 MHz |
| Logic Blocks (LABs) | — | 16 |
| Programmability | — | EEPROM, in-system programmable via JTAG |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |