EPM9320RC208-20N vs EPM9320ARC208-10 Comparison

Detailed side-by-side comparison of EPM9320RC208-20N by Altera and EPM9320ARC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9320ARC208-10 EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ Last Time Buy

Specification Comparison

Parameter EPM9320RC208-20N EPM9320ARC208-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Device Family MAX 9000 MAX 9000
Logic Type Complex Programmable Logic Device (CPLD) —
Usable Gates 6,000 6,000
Macro Cells 320 —
Logic Array Blocks 20 —
Maximum Pin-to-Pin Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage 5.0 V 5.0 V
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
User I/O Pins 168 —
Package 208-pin RQFP (PowerQuad II) RQFP-208 (Power Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Lead Finish [DATA_NEEDED: lead finish] —
MSL Level [DATA_NEEDED: MSL level] —
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 320
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency — 144.9 MHz
Logic Blocks (LABs) — 16
Programmability — EEPROM, in-system programmable via JTAG
JTAG Support — IEEE Std. 1149.1 compliant
Speed/Power Optimization — Per-macrocell programmable, 50% power mode available

Datasheets & Resources

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