EPM9320RI208-10N vs EPM9320RI208-20C Vergleich
Detaillierter Direktvergleich von EPM9320RI208-10N von Altera und EPM9320RI208-20C von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320RI208-20C - 320-Macrocell MAX 9000 CPLD, 5V, 208-RQFP | Intel
EPM9320RI208-20C ObsoleteSpezifikationsvergleich
| Parameter | EPM9320RI208-10N | EPM9320RI208-20C |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $22,10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | Complex Programmable Logic Device (CPLD) | EE PLD / CPLD |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | 20 ns |
| Maximum System Clock Frequency | 100 MHz | — |
| Versorgungsspannung | 5 V | — |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | — |
| Gehäuse | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (Plastic Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG/ISP) | Yes (5.0 V ISP via JTAG) |
| Betriebstemperaturbereich | -40C to +85C (industrial) | — |
| RoHS-Status | Compliant (N suffix = lead-free) | — |
| Lead Finish | Lead-free (matte tin) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Logic Elements / Macrocells | — | 320 |
| Number of Flip-Flops | — | 484 |
| Maximum Internal Clock Frequency | — | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5.0 V |
| Programmable Interface | — | JTAG (IEEE Std. 1149.1) BST |
| Technology | — | CMOS EEPROM |
| Operating Temperature (Industrial) | — | -40C to +85C |
| Lead-Free / RoHS | — | Information not confirmed from verified data [DATA_NEEDED: RoHS status] |