EPM9320RI208-10N vs EPM9320RI208-20C 对比

详细并排对比 EPM9320RI208-10N 出自 Altera 和 EPM9320RI208-20C 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N ✓ 量产中

规格对比

参数 EPM9320RI208-10N EPM9320RI208-20C
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $27.20 $22.10
Family MAX 9000 MAX 9000
Device Type Complex Programmable Logic Device (CPLD) EE PLD / CPLD
Usable Gates 6,000 6,000
Macro Cells 320 —
Logic Array Blocks (LABs) 20 16
Pin-to-Pin Propagation Delay (tPD) 10 ns 20 ns
Maximum System Clock Frequency 100 MHz —
电源电压 5 V —
I/O Voltage 5 V —
User I/O Pins 160 —
封装 208-pin RQFP (PowerQuad II) 208-pin RQFP (Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes (JTAG/ISP) Yes (5.0 V ISP via JTAG)
工作温度范围 -40C to +85C (industrial) —
RoHS 状态 Compliant (N suffix = lead-free) —
Lead Finish Lead-free (matte tin) —
MSL 等级 [DATA_NEEDED: MSL level] —
Logic Elements / Macrocells — 320
Number of Flip-Flops — 484
Maximum Internal Clock Frequency — 100 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5.0 V
Programmable Interface — JTAG (IEEE Std. 1149.1) BST
Technology — CMOS EEPROM
Operating Temperature (Industrial) — -40C to +85C
Lead-Free / RoHS — Information not confirmed from verified data [DATA_NEEDED: RoHS status]

数据手册与资源

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