EPM9320RI208-20 vs EPM9320RI208-20N Vergleich

Detaillierter Direktvergleich von EPM9320RI208-20 von Intel und EPM9320RI208-20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320RI208-20 EPM9320RI208-20N
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,95 $0,00
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 320 320
Usable Gates 6,000 —
Propagation Delay (tPD) 20 ns 20 ns
Maximum Operating Frequency 100 MHz —
Supply Voltage (VCC) 5.0 V 5.0 V
Logic Elements / LABs 20 Logic Array Blocks (16 macro cells each) —
Programmable Interconnect Programmable Interconnect Array (PIA) —
In-System Programmability Yes - IEEE 1149.1 JTAG, 5.0-V ISP Yes, 5.0 V ISP via JTAG
Dedicated Input Pins 4 (low-skew global) 4 (low-skew global distribution)
User I/O Pins [DATA_NEEDED: I/O pin count for 208-pin RQFP] —
Gehäuse 208-pin RQFP (Power Quad Flat Pack) 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature Grade Industrial —
Technology CMOS EEPROM —
Montageart Surface Mount Surface Mount
MSL-Level [DATA_NEEDED: MSL rating] —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000 (EPM9320)
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Flip-Flops — 484
I/O Voltage Tolerance — 3.3 V or 5 V configurable
Package Lead Pitch — 0.500 mm
Number of Terminals — 208
Betriebstemperaturbereich — -40C to +85C (Industrial)
JTAG Interface — IEEE Std. 1149.1 compliant
Configuration Memory — EEPROM (non-volatile)
Minimum DC Input on I/O Pins — -0.5 V
Minimum DC Input on Dedicated Inputs — -0.3 V
Input Undershoot/ Overshoot — -2.0 V / 7.0 V for <20 ns (no-load)

Datenblätter & Ressourcen

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