EPM9320RI208-20 vs EPM9320RI208-20N Comparison

Detailed side-by-side comparison of EPM9320RI208-20 by Intel and EPM9320RI208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RI208-20 EPM9320RI208-20N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $18.95 $0.00
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 320 320
Usable Gates 6,000 β€”
Propagation Delay (tPD) 20 ns 20 ns
Maximum Operating Frequency 100 MHz β€”
Supply Voltage (VCC) 5.0 V 5.0 V
Logic Elements / LABs 20 Logic Array Blocks (16 macro cells each) β€”
Programmable Interconnect Programmable Interconnect Array (PIA) β€”
In-System Programmability Yes - IEEE 1149.1 JTAG, 5.0-V ISP Yes, 5.0 V ISP via JTAG
Dedicated Input Pins 4 (low-skew global) 4 (low-skew global distribution)
User I/O Pins [DATA_NEEDED: I/O pin count for 208-pin RQFP] β€”
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature Grade Industrial β€”
Technology CMOS EEPROM β€”
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL rating] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Device Family β€” MAX 9000 (EPM9320)
Logic Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Flip-Flops β€” 484
I/O Voltage Tolerance β€” 3.3 V or 5 V configurable
Package Lead Pitch β€” 0.500 mm
Number of Terminals β€” 208
Operating Temperature Range β€” -40C to +85C (Industrial)
JTAG Interface β€” IEEE Std. 1149.1 compliant
Configuration Memory β€” EEPROM (non-volatile)
Minimum DC Input on I/O Pins β€” -0.5 V
Minimum DC Input on Dedicated Inputs β€” -0.3 V
Input Undershoot/ Overshoot β€” -2.0 V / 7.0 V for <20 ns (no-load)

Datasheets & Resources

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