EPM9560R1208-20 vs EPM9480RC240-20 Vergleich

Detaillierter Direktvergleich von EPM9560R1208-20 von Altera und EPM9480RC240-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560R1208-20 EPM9480RC240-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $22,40 $8,40
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 6,000 10,000
Macrocells 560 480
Logic Array Blocks 52 (typical for 560 macrocells) —
Maximum User I/O 212 —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Technology CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Betriebstemperatur 0C to +70C (commercial) —
Gehäuse R-1208 (BGA-style fine-pitch) 240-RQFP (32x32 mm, FQFP, Gull Wing)
Montageart Surface Mount —
Process Technology CMOS EEPROM, third-generation MAX architecture CMOS EEPROM
Architecture Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) —
Boundary-Scan Test JTAG IEEE Std. 1149.1 —
Configuration Memory On-chip EEPROM (non-volatile) —
RoHS-Status [DATA_NEEDED: confirm via current distributor data] [DATA_NEEDED: RoHS status]
Logic Elements — 30
User I/O Pins — 175
Number of Terminals — 240
Maximum Propagation Delay (tpd) — 20 ns
Maximum Internal Frequency (fMAX, related -C variant) — 100 MHz
Programmable Flip-Flops (family) — 676
Internal Supply Voltage — 4.75 V to 5.25 V
I/O Signaling Levels — 3.3 V or 5 V (configurable)
Programming Interface — In-System Programmable (ISP) via IEEE 1149.1 JTAG
Operating Temperature Grade — Commercial
Terminal Form — Gull Wing

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