EPM9560R1208-20 vs EPM9480RC240-20 Comparación
Comparación detallada lado a lado de EPM9560R1208-20 por Altera y EPM9480RC240-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560R1208-20 | EPM9480RC240-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,40 | $8,40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 10,000 |
| Macrocells | 560 | 480 |
| Logic Array Blocks | 52 (typical for 560 macrocells) | — |
| Maximum User I/O | 212 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Encapsulado | R-1208 (BGA-style fine-pitch) | 240-RQFP (32x32 mm, FQFP, Gull Wing) |
| Tipo de montaje | Surface Mount | — |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | — |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Estado RoHS | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 30 |
| User I/O Pins | — | 175 |
| Number of Terminals | — | 240 |
| Maximum Propagation Delay (tpd) | — | 20 ns |
| Maximum Internal Frequency (fMAX, related -C variant) | — | 100 MHz |
| Programmable Flip-Flops (family) | — | 676 |
| Internal Supply Voltage | — | 4.75 V to 5.25 V |
| I/O Signaling Levels | — | 3.3 V or 5 V (configurable) |
| Programming Interface | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | Gull Wing |