EPM9560R1208-20 vs EPM9560RI208-20 Vergleich

Detaillierter Direktvergleich von EPM9560R1208-20 von Altera und EPM9560RI208-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560R1208-20 EPM9560RI208-20
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $22,40 $21,10
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 6,000 12,000
Macrocells 560 —
Logic Array Blocks 52 (typical for 560 macrocells) —
Maximum User I/O 212 —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Technology CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (IEEE Std. 1149.1 JTAG)
Betriebstemperatur 0C to +70C (commercial) [DATA_NEEDED: operating temperature range grade]
Gehäuse R-1208 (BGA-style fine-pitch) 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm
Montageart Surface Mount Surface Mount
Process Technology CMOS EEPROM, third-generation MAX architecture CMOS EEPROM
Architecture Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) Multiple Array MatriX (MAX) - third generation
Boundary-Scan Test JTAG IEEE Std. 1149.1 —
Configuration Memory On-chip EEPROM (non-volatile) —
RoHS-Status [DATA_NEEDED: confirm via current distributor data] [DATA_NEEDED: RoHS compliance status]
Macro Cells — 560
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 212
Pin-to-Pin Propagation Delay (tPD) — 20 ns
Counter Frequency (fCNT) — 100 MHz
Supply Voltage (VCC) — 5.0 V

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern