EPM9560R1208-20 vs EPM9560RI208-20 Comparison

Detailed side-by-side comparison of EPM9560R1208-20 by Altera and EPM9560RI208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560R1208-20 EPM9560RI208-20
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $22.40 $21.10
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 6,000 12,000
Macrocells 560 β€”
Logic Array Blocks 52 (typical for 560 macrocells) β€”
Maximum User I/O 212 β€”
Propagation Delay (tPD) 20 ns β€”
Maximum Frequency (fMAX) 125 MHz β€”
Supply Voltage (VCCINT/VCCIO) 5.0 V β€”
Technology CMOS EEPROM β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (IEEE Std. 1149.1 JTAG)
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature range grade]
Package R-1208 (BGA-style fine-pitch) 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm
Mounting Type Surface Mount Surface Mount
Process Technology CMOS EEPROM, third-generation MAX architecture CMOS EEPROM
Architecture Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) Multiple Array MatriX (MAX) - third generation
Boundary-Scan Test JTAG IEEE Std. 1149.1 β€”
Configuration Memory On-chip EEPROM (non-volatile) β€”
RoHS Status [DATA_NEEDED: confirm via current distributor data] [DATA_NEEDED: RoHS compliance status]
Macro Cells β€” 560
Logic Array Blocks (LABs) β€” 16
Maximum User I/O Pins β€” 212
Pin-to-Pin Propagation Delay (tPD) β€” 20 ns
Counter Frequency (fCNT) β€” 100 MHz
Supply Voltage (VCC) β€” 5.0 V

Datasheets & Resources

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