EPM9560RC208-10N vs EPM9560RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9560RC208-10N von Intel und EPM9560RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel
EPM9560RC208-10N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9560RC208-10N | EPM9560RC208-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $175,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Macro Cells | 560 | 560 macro cells |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay (tPD1) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Bank Voltage (VCCIO) | 5.0 V | — |
| Gehäuse | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Versorgungsspannung | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |