EPM9560RC208-20 vs EPM9560RC208-18 Vergleich
Detaillierter Direktvergleich von EPM9560RC208-20 von Intel und EPM9560RC208-18 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC208-20 | EPM9560RC208-18 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Ende des Lebenszyklus |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Macrocells | 560 | 560 macrocells |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks | 35 | — |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximale Taktfrequenz | 100 MHz | — |
| Versorgungsspannung | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Gehäuse | 208-pin RQFP (28x28 mm) | 208-pin RQFP (Power Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Standards | 5.0 V TTL/CMOS compatible | — |
| Flip-Flops | 772 | 772 flip-flops |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Propagation Delay (tPD) | — | 18 ns (speed grade -18) |
| Maximum Operating Frequency | — | 117.6 MHz (family -15 grade reference) |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| User I/O Lines | — | 149 I/O lines |
| Package JESD-30 Code | — | S-PQFP-G208 |
| Configuration Memory | — | EEPROM (non-volatile, no external config PROM) |
| Technology | — | CMOS |
| Lebenszyklusstatus | — | EOL / mature (per Altera product discontinuance notice) |