EPM9560RC208-20N vs EPM9560WC208-20C Vergleich
Detaillierter Direktvergleich von EPM9560RC208-20N von Intel und EPM9560WC208-20C von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC208-20N | EPM9560WC208-20C |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $140,00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EE PLD) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Gehäuse | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| User I/O Pins | 149 | 149 |
| Versorgungsspannung | 5.0 V | 3.3 V or 5 V (configurable I/O) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Montageart | Surface Mount | Surface Mount (Ceramic QFP) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | Lead-free (N suffix) | ROHS3 Compliant (per fpgalink listing) |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Series | — | EPM9560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximale Taktfrequenz | — | [DATA_NEEDED: fMAX value not in verified data] |
| Process Technology | — | CMOS, Electrically Erasable |
| Pin-Anzahl | — | 208 |
| Programming Interface | — | JTAG BST (in-system programmable) |
| Operating Temperature Grade | — | Commercial (C suffix) |
| Moisture Sensitivity Level | — | MSL 3 (168 Hours) |