EPM9560RC208-7 vs EPM9560SRC208-7 Vergleich

Detaillierter Direktvergleich von EPM9560RC208-7 von Altera und EPM9560SRC208-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560RC208-7 EPM9560SRC208-7
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,90 $52,00
Family MAX 9000 MAX 9000
Device Type EPLD / CPLD EPLD (Erasable Programmable Logic Device)
Usable Gates 560 12,000
Macrocells 16 560
Logic Array Blocks (LABs) 4 16
User I/O Pins 208 —
Pin-to-Pin Delay (tPD) 7 ns (speed grade -7) —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] —
Supply Voltage (VCCINT) 5.0 V —
Supply Voltage (VCCIO) 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) —
Process Technology 0.65 um CMOS EEPROM —
Configuration Memory Non-volatile on-chip EEPROM (no boot PROM required) —
Programming Interface JTAG (IEEE 1149.1) + Altera ISP —
Gehäuse 208-pin Power Quad Flat Pack (RQFP-208) 208-pin SQFP (Surface-mount Quad Flat Pack)
Betriebstemperatur 0C to +70C (commercial) / -40C to +85C (industrial) —
Output Drive Current 160 mA DC sink per pin —
RoHS-Status Compliant (ROHS3 per distributor listing) [DATA_NEEDED: per part marking / distributor listing]
Maximum I/O Pins — 212
Pin-to-Pin Logic Delay (tPD) — 7.0 ns
Maximum Frequency (fCNT) — [DATA_NEEDED: fCNT for -7 speed grade]
Supply Voltage (VCC) — 5.0 V (single supply)
Programming Method — In-system via IEEE Std 1149.1 JTAG
Betriebstemperaturbereich — -40 °C to +85 °C (industrial)
Technology — CMOS, EEPROM-based
Montageart — Surface Mount
MSL-Level — [DATA_NEEDED: not stated in mature datasheet]

Datenblätter & Ressourcen

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