EPM9560RC210-20 vs EPM9560RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9560RC210-20 von Altera und EPM9560RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera
EPM9560RC210-20 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9560RC210-20 | EPM9560RC208-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $60,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| Gehäuse | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Clock-to-Output (tCO) | 12 ns | — |
| Maximum User I/O | [DATA_NEEDED: 212 I/O per datasheet, package-dependent] | — |
| Versorgungsspannung | 5 V | 5.0 V |
| Process Technology | 0.65 um EEPROM | — |
| In-System Programmability | Yes (MAX+PLUS II flow) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Betriebstemperatur | [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] | [DATA_NEEDED: operating temperature range] |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | RoHS3 Compliant (per supplier listing) | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |