EPM9560RC210-20 vs EPM9560RC208-15 Comparación
Comparación detallada lado a lado de EPM9560RC210-20 por Altera y EPM9560RC208-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC210-20 | EPM9560RC208-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $60,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| Encapsulado | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Clock-to-Output (tCO) | 12 ns | — |
| Maximum User I/O | [DATA_NEEDED: 212 I/O per datasheet, package-dependent] | — |
| Tensión de alimentación | 5 V | 5.0 V |
| Process Technology | 0.65 um EEPROM | — |
| In-System Programmability | Yes (MAX+PLUS II flow) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | RoHS3 Compliant (per supplier listing) | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |