EPM9560RC240-15C vs EPM9560RC240-10 Vergleich
Detaillierter Direktvergleich von EPM9560RC240-15C von Intel und EPM9560RC240-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC240-15C | EPM9560RC240-10 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | Complex Programmable Logic Device (CPLD) |
| Usable Gates | 12,000 | 12,000 gates |
| Macrocells | 560 | — |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | 192 |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| Versorgungsspannung | 5.0 V | 5 V |
| Operating Voltage Range | 3.3 V or 5 V | — |
| Gehäuse | 240-pin RQFP (PowerQuad II) | 240-pin RQFP (PowerQuad) |
| Terminal Pitch | 0.5 mm | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 12 |
| Maximum System Frequency | — | 144.9 MHz |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Technology | — | CMOS EEPROM |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | — | 3 (168 Hours) |
| Configuration Memory | — | Non-volatile EEPROM (instant-on) |
| Manufacturer Standard Lead Time | — | 1-7 Days (distributor stock) |