EPM9560RC304-10 vs EPM9560RC304-15C Vergleich
Detaillierter Direktvergleich von EPM9560RC304-10 von Intel und EPM9560RC304-15C von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoleteSpezifikationsvergleich
| Parameter | EPM9560RC304-10 | EPM9560RC304-15C |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,60 | $24,50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD / EPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | — |
| Usable Gates | 16000 | 12,000 |
| Logic Elements | 560 | — |
| Gehäuse | RQFP-304 (RC) | 304-pin RQFP |
| Pin-Anzahl | 304 | — |
| Pin-to-Pin Propagation Delay | 12 ns | — |
| Speed Grade | -10 | — |
| Versorgungsspannung | 5 V | 5.0 V |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (Commercial) |
| User I/O Pins | 304 (package-limited) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Programming Method | JTAG in-system (ISP) | — |
| Process Technology | 0.65 µm CMOS EEPROM | CMOS EEPROM |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 (168 Hours) | — |
| RoHS-Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum |