EPM9560RC304-15F vs EPM9560RC304-2 Vergleich
Detaillierter Direktvergleich von EPM9560RC304-15F von Altera und EPM9560RC304-2 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteIntel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteSpezifikationsvergleich
| Parameter | EPM9560RC304-15F | EPM9560RC304-2 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,75 | $55,00 |
| Device Family | MAX 9000 | — |
| Series | EPM9560 | — |
| Macrocells | 560 | [DATA_NEEDED: macrocell count] |
| Usable Gates | 12,000 | Approximately 12,000 |
| Propagation Delay (tpd) | 16.6 ns (max) | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Core Supply Voltage | 5.0 V | 5.0 V |
| User I/O Pins | 212 | 304 |
| Dedicated Inputs | 4 | — |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | 16 |
| Gehäuse | RQFP-304 (304-pin Plastic QFP) | 304-pin RQFP (RC) |
| Programming Technology | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) | EEPROM (in-system programmable) |
| Architecture | Multiple Array MatriX (MAX) with PIA interconnect | Multiple Array MatriX (MAX) - third generation |
| Boundary Scan Test (BST) | Yes, JTAG-compliant | — |
| Betriebstemperatur | -40C to +85C (industrial) | Commercial (0C to +70C) |
| Process Technology | High-performance CMOS, EEPROM-based | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | [DATA_NEEDED: rohs status - not stated in source] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (EPLD - Erasable PLD) |
| Speed Grade | — | -2 |
| I/O Supply Voltage | — | 5.0 V |
| JTAG Support | — | IEEE Std. 1149.1 (boundary-scan + ISP) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |