EPM9560RC304-2 vs EPM9560RC304-15F Vergleich
Detaillierter Direktvergleich von EPM9560RC304-2 von Intel und EPM9560RC304-15F von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteAltera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteSpezifikationsvergleich
| Parameter | EPM9560RC304-2 | EPM9560RC304-15F |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $55,00 | $18,75 |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD - Erasable PLD) | — |
| Usable Gates | Approximately 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | 16 (40 macrocells each) |
| Macrocells | [DATA_NEEDED: macrocell count] | 560 |
| User I/O Pins | 304 | 212 |
| Gehäuse | 304-pin RQFP (RC) | RQFP-304 (304-pin Plastic QFP) |
| Speed Grade | -2 | — |
| Core Supply Voltage | 5.0 V | 5.0 V |
| I/O Supply Voltage | 5.0 V | — |
| Programming Technology | EEPROM (in-system programmable) | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) | — |
| Betriebstemperatur | Commercial (0C to +70C) | -40C to +85C (industrial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status - not stated in source] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) with PIA interconnect |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Device Family | — | MAX 9000 |
| Series | — | EPM9560 |
| Propagation Delay (tpd) | — | 16.6 ns (max) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Dedicated Inputs | — | 4 |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Process Technology | — | High-performance CMOS, EEPROM-based |
| MSL-Level | — | 3 (168 hours) |