EPM9560RC304-2 vs EPM9560RC304-15F Comparison
Detailed side-by-side comparison of EPM9560RC304-2 by Intel and EPM9560RC304-15F by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteAltera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteSpecification Comparison
| Parameter | EPM9560RC304-2 | EPM9560RC304-15F |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $55.00 | $18.75 |
| Family | MAX 9000 | β |
| Device Type | CPLD (EPLD - Erasable PLD) | β |
| Usable Gates | Approximately 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | 16 (40 macrocells each) |
| Macrocells | [DATA_NEEDED: macrocell count] | 560 |
| User I/O Pins | 304 | 212 |
| Package | 304-pin RQFP (RC) | RQFP-304 (304-pin Plastic QFP) |
| Speed Grade | -2 | β |
| Core Supply Voltage | 5.0 V | 5.0 V |
| I/O Supply Voltage | 5.0 V | β |
| Programming Technology | EEPROM (in-system programmable) | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) | β |
| Operating Temperature | Commercial (0C to +70C) | -40C to +85C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status - not stated in source] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) with PIA interconnect |
| Configuration Memory | On-chip EEPROM (non-volatile) | β |
| Device Family | β | MAX 9000 |
| Series | β | EPM9560 |
| Propagation Delay (tpd) | β | 16.6 ns (max) |
| Maximum Internal Frequency | β | 117.6 MHz |
| Dedicated Inputs | β | 4 |
| Boundary Scan Test (BST) | β | Yes, JTAG-compliant |
| Process Technology | β | High-performance CMOS, EEPROM-based |
| MSL Level | β | 3 (168 hours) |