EPM9560RC304-20N vs EPM9560RC304C-3 Vergleich
Detaillierter Direktvergleich von EPM9560RC304-20N von Altera und EPM9560RC304C-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560RC304C-3 - MAX 9000 CPLD, 560 Macrocells, 304-Pin RBGGA | Altera
EPM9560RC304C-3 ObsoleteSpezifikationsvergleich
| Parameter | EPM9560RC304-20N | EPM9560RC304C-3 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $95,00 |
| Device Family | MAX 9000 (EPM9560) | — |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | CPLD (EPLD) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 20 | — |
| User I/O Pins | 212 | 212 |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum System Frequency | 100 MHz | — |
| Core Supply Voltage | 5.0 V | — |
| I/O Voltage Support | 3.3 V or 5.0 V configurable | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Gehäuse | 304-pin RQFP (PowerQuad) | RBGGA-304 (Ceramic Ball Grid Array) |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | RoHS3 Compliant | unknown (legacy part, pre-RoHS era) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 3 (168 Hours) | — |
| Manufacturer Standard Lead Time | 1-7 Days (distributor listing) | — |
| Family | — | MAX 9000 |
| Macrocells (Logic Elements) | — | 560 |
| Pin-Anzahl | — | 304 |
| Speed Grade | — | -3 (3 ns pin-to-pin, commercial) |
| Betriebstemperatur | — | 0 C to +70 C (Commercial) |
| Versorgungsspannung | — | 5 V |
| Programmability | — | In-system, non-volatile EEPROM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Logic Blocks | — | Logic Array Blocks (LABs) with PIA interconnect |