EPM9560RC304-5 vs EPM9560RCRC304-15 Vergleich
Detaillierter Direktvergleich von EPM9560RC304-5 von Altera und EPM9560RCRC304-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RC304-5 | EPM9560RCRC304-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Device Type | Complex Programmable Logic Device (CPLD) / EPLD | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| Versorgungsspannung | 5.0 V | 5.0 V |
| Speed Grade | -5 (fastest grade in family) | — |
| Gehäuse | 304-pin RQFP (PowerQuad II) | 304-pin RQFP (PowerQuad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | — |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 3 (168 Hours) | — |
| RoHS-Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Manufacturer Standard Lead Time | 1-7 Days (distributor listing) | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: propagation delay] | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: number of LABs] | [DATA_NEEDED: LAB count] |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 117.6 MHz |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability (ISP) | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Number of User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |
| Lead Finish | — | [DATA_NEEDED: lead finish] |