EPM9560RC304-5 vs EPM9560RCRC304-15 对比

详细并排对比 EPM9560RC304-5 出自 Altera 和 EPM9560RCRC304-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC304-5 EPM9560RCRC304-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $0.00
Device Family MAX 9000 (EPM9560) MAX 9000 (EPM9560)
Device Type Complex Programmable Logic Device (CPLD) / EPLD —
Usable Gates 12,000 12,000
Macrocells 560 —
Maximum Operating Frequency 117.6 MHz (family -15 grade reference) —
电源电压 5.0 V 5.0 V
Speed Grade -5 (fastest grade in family) —
封装 304-pin RQFP (PowerQuad II) 304-pin RQFP (PowerQuad Flat Pack)
安装类型 Surface Mount Surface Mount
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes (JTAG ISP) —
湿敏等级(MSL) 3 (168 Hours) —
RoHS 状态 ROHS3 Compliant [DATA_NEEDED: RoHS status]
Manufacturer Standard Lead Time 1-7 Days (distributor listing) —
工作温度范围 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Number of I/O Pins [DATA_NEEDED: number of user I/O pins] —
Propagation Delay (tPD) [DATA_NEEDED: propagation delay] —
Logic Array Blocks (LABs) [DATA_NEEDED: number of LABs] [DATA_NEEDED: LAB count]
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Maximum Frequency — 117.6 MHz
Configuration Memory — EEPROM (non-volatile, in-system programmable)
In-System Programmability (ISP) — Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface — IEEE Std. 1149.1 (built-in)
Number of User I/O Pins — [DATA_NEEDED: user I/O pin count]
Architecture — Third-generation Multiple Array MatriX (MAX)
Lead Finish — [DATA_NEEDED: lead finish]

数据手册与资源

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