EPM9560RI208-10N vs EPM9560RI208-15N Vergleich
Detaillierter Direktvergleich von EPM9560RI208-10N von Altera und EPM9560RI208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RI208-10N | EPM9560RI208-15N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $61,75 | $19,45 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX), 3rd generation |
| Usable Gates | 12,000 | — |
| Macro Cells | 560 | — |
| Register Bits | 12,160 | — |
| User I/Os | 212 | 216 (per DigiChip specification; see _validation_note) |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Maximum Frequency | 100 MHz to 125 MHz | — |
| Versorgungsspannung | 5 V | 5.0 V |
| Gehäuse | 208-pin RQFP (PQFP) | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Betriebstemperatur | -40C to +85C (Industrial grade, "RI" suffix) | 0C to 70C (Commercial) |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | — |
| MSL-Level | 3 (168 Hours) | — |
| RoHS-Status | ROHS3 Compliant (per fpgalink) | [DATA_NEEDED: RoHS status] |
| Configuration Memory | On-chip EEPROM (non-volatile) | CMOS EEPROM, in-system programmable |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Speed Grade | — | -15 |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |