EPM9560RI208-10N vs EPM9560RI208-15N 对比

详细并排对比 EPM9560RI208-10N 出自 Altera 和 EPM9560RI208-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RI208-10N EPM9560RI208-15N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $61.75 $19.45
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Architecture CMOS EEPROM-based Multiple Array MatriX (MAX) Multiple Array MatriX (MAX), 3rd generation
Usable Gates 12,000 —
Macro Cells 560 —
Register Bits 12,160 —
User I/Os 212 216 (per DigiChip specification; see _validation_note)
Pin-to-Pin Delay 10 ns (speed grade -10) —
Maximum Frequency 100 MHz to 125 MHz —
电源电压 5 V 5.0 V
封装 208-pin RQFP (PQFP) 208-pin RQFP (Ruggedized Quad Flat Pack)
工作温度 -40C to +85C (Industrial grade, "RI" suffix) 0C to 70C (Commercial)
Programming Method In-system via IEEE 1149.1 (JTAG) —
MSL 等级 3 (168 Hours) —
RoHS 状态 ROHS3 Compliant (per fpgalink) [DATA_NEEDED: RoHS status]
Configuration Memory On-chip EEPROM (non-volatile) CMOS EEPROM, in-system programmable
Manufacturer — Altera (Intel Programmable Solutions Group)
Device Family — MAX 9000
Total Pins — 356 (per third-party catalog; see _validation_note)
Package Pin Count — 208
Terminal Form — Gull Wing
Package Code — HFQFP
Maximum Internal Frequency — 145 MHz
Propagation Delay (tPD) — 11.4 ns (15 ns speed grade)
Speed Grade — -15
Temperature Grade — Industrial (per Vyrian/Partstack listings)
Logic Family — CMOS
Programming Interface — IEEE 1149.1 JTAG, 5.0-V in-system

数据手册与资源

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