EPM9560RI208-15 vs EPM9560RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9560RI208-15 von Intel und EPM9560RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560RI208-15 | EPM9560RC208-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $20,10 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Third-generation Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | — |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| Anzahl der Pins | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| Betriebstemperatur | 0 °C to 70 °C (industrial grade; per package suffix R) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| RoHS-Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 3 (168 hours) | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | — | 12,000 gates |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Versorgungsspannung | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Gehäuse | — | 208-pin RQFP (Power Quad Flat Pack) |
| Montageart | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |