EPM9560RI208-15 vs EPM9560RC208-15 比較
詳細な並列比較: EPM9560RI208-15 メーカー: Intel および EPM9560RC208-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560RI208-15 | EPM9560RC208-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $20.10 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Third-generation Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | — |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| ピン数 | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| 動作温度 | 0 °C to 70 °C (industrial grade; per package suffix R) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| RoHS ステータス | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| 湿気感度レベル（MSL） | 3 (168 hours) | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | — | 12,000 gates |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| 電源電圧 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| パッケージ | — | 208-pin RQFP (Power Quad Flat Pack) |
| 実装タイプ | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |