EPM9560RI208-15N vs EPM9560RI208-20W Vergleich

Detaillierter Direktvergleich von EPM9560RI208-15N von Altera und EPM9560RI208-20W von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560RI208-15N EPM9560RI208-20W
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $19,45 $48,75
Manufacturer Altera (Intel Programmable Solutions Group) —
Device Family MAX 9000 —
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX), 3rd generation Third-generation Multiple Array MatriX (MAX)
Configuration Memory CMOS EEPROM, in-system programmable —
Gehäuse 208-pin RQFP (Ruggedized Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Total Pins 356 (per third-party catalog; see _validation_note) —
Package Pin Count 208 —
Terminal Form Gull Wing —
Package Code HFQFP —
User I/Os 216 (per DigiChip specification; see _validation_note) —
Maximum Internal Frequency 145 MHz —
Propagation Delay (tPD) 11.4 ns (15 ns speed grade) —
Speed Grade -15 -20
Versorgungsspannung 5.0 V 5.0 V
Betriebstemperatur 0C to 70C (Commercial) -40C to +85C (Industrial)
Temperature Grade Industrial (per Vyrian/Partstack listings) —
Logic Family CMOS —
Programming Interface IEEE 1149.1 JTAG, 5.0-V in-system —
RoHS-Status [DATA_NEEDED: RoHS status] —
Family — MAX 9000
Usable Gates — 12,000
Macrocells — 560
Logic Array Blocks (LABs) — 16 LABs of 40 macrocells each
User I/O Pins — 212
Pin-to-Pin Delay (tPD) — 20 ns
Counter Frequency (fCNT) — 100 MHz
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Programming Technology — CMOS EEPROM

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