EPM9560RI208-20W vs EPM9560RI208-15N Vergleich

Detaillierter Direktvergleich von EPM9560RI208-20W von Intel und EPM9560RI208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9560RI208-20W EPM9560RI208-15N
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $48,75 $19,45
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Usable Gates 12,000 —
Macrocells 560 —
Logic Array Blocks (LABs) 16 LABs of 40 macrocells each —
User I/O Pins 212 —
Pin-to-Pin Delay (tPD) 20 ns —
Counter Frequency (fCNT) 100 MHz —
Speed Grade -20 -15
Versorgungsspannung 5.0 V 5.0 V
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Programming Technology CMOS EEPROM —
Gehäuse 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Ruggedized Quad Flat Pack)
Betriebstemperatur -40C to +85C (Industrial) 0C to 70C (Commercial)
Architecture Third-generation Multiple Array MatriX (MAX) Multiple Array MatriX (MAX), 3rd generation
Manufacturer — Altera (Intel Programmable Solutions Group)
Device Family — MAX 9000
Configuration Memory — CMOS EEPROM, in-system programmable
Total Pins — 356 (per third-party catalog; see _validation_note)
Package Pin Count — 208
Terminal Form — Gull Wing
Package Code — HFQFP
User I/Os — 216 (per DigiChip specification; see _validation_note)
Maximum Internal Frequency — 145 MHz
Propagation Delay (tPD) — 11.4 ns (15 ns speed grade)
Temperature Grade — Industrial (per Vyrian/Partstack listings)
Logic Family — CMOS
Programming Interface — IEEE 1149.1 JTAG, 5.0-V in-system
RoHS-Status — [DATA_NEEDED: RoHS status]

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