ICS570B vs ICS570A Vergleich

Detaillierter Direktvergleich von ICS570B von Renesas Electronics und ICS570A von Renesas Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Renesas Electronics
ICS570B ICS570B - 170 MHz 3.3 V PLL Clock Buffer | Renesas

ICS570B - 170 MHz 3.3 V PLL Clock Buffer | Renesas

ICS570B Unknown
Renesas Electronics
ICS570A ICS570A - 170MHz Zero Delay Buffer | Renesas | Clocking

ICS570A - 170MHz Zero Delay Buffer | Renesas | Clocking

ICS570A ✓ Aktiv

Spezifikationsvergleich

Parameter ICS570B ICS570A
Marke Renesas Electronics Renesas Electronics
Kategorie Clock & Timing Clock & Timing
Lebenszyklusstatus Unknown Aktiv
Product Type Fanout distribution, spread-spectrum clock generator and zero-delay buffer Multiplier and Zero Delay Buffer
Clock Generator Architecture Proprietary analog/digital phase-locked loop —
Maximum Output Clock Frequency 170 MHz 170 MHz
Recommended Supply Voltage 3.3 V —
Multiplication Ratios 0.5x to 32x, 14 selectable ratios —
Maximum Input-to-Output Skew 300 ps maximum for outputs above 60 MHz —
Gehäuse 8-pin SOIC, 0.154 in (3.90 mm) width 8-pin SOIC, 0.154 inch body width, 3.90 mm width
Montageart Surface mount Surface mount
Input Duty-Cycle Recovery Supported —
Fanout Function Supported —
Spread-Spectrum Clock Generation Supported —
Output Frequency at 3.3 V Up to 170 MHz —
Betriebstemperaturbereich [DATA_NEEDED: operating temperature range] —
Versorgungsstrom [DATA_NEEDED: supply current] —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lebenszyklusstatus [DATA_NEEDED: active or lifecycle phase] —
Termination Condition 27 ohm termination resistor with 15 pF loads on CLK and CLK/2, typical jitter measurement at 25 C —
Manufacturer — Renesas Electronics Corporation
Supply Voltage Version — 5 V version
Multiplier Choices — 14 choices from 0.5x to 32x
Input-to-Output Skew — 300 ps maximum for outputs above 60 MHz
Clock Architecture — Analog/digital PLL-based zero-delay buffer
Output Functions — Clock multiplication and fanout distribution
Input Clock Duty-Cycle Recovery — Supported
Lead-Free Package — Available for A and B versions
Manufacturer Document Identifier — 570 datasheet
Jitter Measurement Temperature — 25 °C
Jitter Test Termination — 27 ohm termination resistor
Jitter Test Load — 15 pF on both CLK and CLK/2
REACH Status — [DATA_NEEDED: REACH status]
AEC-Q100 Status — [DATA_NEEDED: AEC-Q100 qualification status]

Datenblätter & Ressourcen

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