IDTADC1210S065HN-C18 vs IDTADC1210S105HN-C18 Vergleich

Detaillierter Direktvergleich von IDTADC1210S065HN-C18 von Renesas Electronics und IDTADC1210S105HN-C18 von Renesas Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Renesas Electronics
IDTADC1210S065HN-C18 IDTADC1210S065HN-C18 - 12-bit 65 MSPS ADC | Renesas (IDT)

IDTADC1210S065HN-C18 - 12-bit 65 MSPS ADC | Renesas (IDT)

IDTADC1210S065HN-C18 Nrnd
Renesas Electronics
IDTADC1210S105HN-C18 IDTADC1210S105HN-C18 - 12-bit 105MSPS ADC, 40-VFQFPN | IDT/Renesas

IDTADC1210S105HN-C18 - 12-bit 105MSPS ADC, 40-VFQFPN | IDT/Renesas

IDTADC1210S105HN-C18 ✓ Aktiv

Spezifikationsvergleich

Parameter IDTADC1210S065HN-C18 IDTADC1210S105HN-C18
Marke Renesas Electronics Renesas Electronics
Kategorie ADC/DAC ADC/DAC
Lebenszyklusstatus NRND Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,05 $21,45
Auflösung 12 bit 12 bit
Number of Channels 1 1
Abtastrate 65 MSPS —
Architecture Pipelined Pipelined
Analog Supply Voltage (VDDA) 3.0 V typical (3.9 V abs max) 3 V (typical)
Digital Output Supply (VDDO) 1.8 V to 3.3 V —
Output Interface CMOS parallel or LVDS DDR (selectable) —
Input Type Single-ended analog input (switched-capacitor) —
Operating Ambient Temperature -40C to +85C —
Junction Temperature (max) 125C —
Storage Temperature -55C to +125C -55 C to +125 C
Gehäuse 40-pin HVQFN (6x6 mm) with exposed thermal pad 40-VFQFPN Exposed Pad
Montageart Surface Mount —
Control Mode Pin-control (CS held HIGH at power-up) and SPI serial —
RoHS-Status Compliant (per Renesas/IDT product family) Compliant (per Renesas product page)
Sample Rate (this grade) — 105 Msps
Maximum Sample Rate (family) — 125 Msps
Analog Input Bandwidth — 600 MHz
SNR — 70 dBFS
SFDR — 86 dBc
Output Supply Voltage (VDDO) — 1.8 V (typical)
Analog Supply Range — 0.4 V to 3.9 V (absolute max)
Power Dissipation — 430 mW at 80 Msps
Eingangsspannungsbereich — 1 Vp-p to 2 Vp-p (flexible)
Digital Output Format — CMOS or LVDS DDR
Output Coding — Offset binary, two's complement, gray code
Configuration Interface — SPI (Serial Peripheral Interface)
Clock Input Division — Divided by 2 internally
Duty Cycle Stabilizer — Integrated
Out-of-Range Detection — Fast OTR flag
Operating Temperature (Tamb) — -40 C to +85 C
Maximum Junction Temperature — 125 C

Datenblätter & Ressourcen

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