MC9S08DZ60AMLF vs MC9S08DZ60ACLF Vergleich
Detaillierter Direktvergleich von MC9S08DZ60AMLF von NXP Semiconductors und MC9S08DZ60ACLF von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
MC9S08DZ60ACLF - 8-bit S08 MCU, 60KB Flash, CAN/LIN, 48-LQFP | NXP
MC9S08DZ60ACLF NrndSpezifikationsvergleich
| Parameter | MC9S08DZ60AMLF | MC9S08DZ60ACLF |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $6,85 |
| Core Processor | S08 (HCS08), 8-bit CISC | — |
| Core Size | 8-Bit | — |
| Maximum CPU Frequency | 40 MHz (20 MHz bus) | — |
| Program Memory Size | 60 KB (60K x 8) Flash | — |
| RAM Size | 4 KB | — |
| Data EEPROM | Embedded EEPROM | — |
| Connectivity | CAN 2.0 A/B (MSCAN), LIN master-capable SCI, SPI, SCI | — |
| ADC Resolution | 12-bit | — |
| ADC Channels | 24-channel (16-channel 12-bit ADC per FindIC overview) | — |
| ADC Conversion Time | 2.5 us | — |
| Analog Comparators | 1 | — |
| Versorgungsspannung | 3.3 V / 5 V | — |
| Interrupt/Reset Sources | Up to 32 | — |
| Debug | On-chip background debug (BGND instruction) | — |
| Gehäuse | 48-LQFP (7x7 mm) | 48-LQFP (7x7 mm) |
| Montageart | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| RoHS-Status | RoHS compliant (per distributor listing) | Compliant |
| Lebenszyklusstatus | NRND (Not Recommended for New Designs) per NXP | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: AEC-Q100 grade range] |
| Core | — | HCS08 (8-bit CISC) |
| Core Frequency | — | 40 MHz (20 MHz bus) |
| Program Memory (Flash) | — | 60 KB (60K x 8) |
| RAM | — | 4 KB |
| EEPROM / Emulated EEPROM | — | Available (size [DATA_NEEDED: EEPROM size]) |
| Operating Voltage | — | 2.7 V to 5.5 V |
| Supply Rails | — | 3.3 V / 5 V |
| ADC | — | 24-channel, 12-bit, 2.5 us conversion |
| CAN | — | 1 x CAN 2.0 A/B |
| LIN | — | Master LIN 2.0 interface |
| Communication Peripherals | — | SCI (SPI), IIC, MSCAN |
| Timer / PWM Channels | — | Multiple (count [DATA_NEEDED: timer/PWM channel count]) |
| LCD Driver | — | Yes (on-chip segment LCD driver) |
| MSL-Level | — | MSL 3 (per JEDEC J-STD-020) |
| Background Debug Mode (BGND) | — | Yes (on-chip emulation/debug) |
| Instruction Set | — | HC08 instruction set with added BGND instruction |