MPC8548ECVTAQGD vs MPC8548EVTAVHD557 Vergleich
Detaillierter Direktvergleich von MPC8548ECVTAQGD von NXP Semiconductors und MPC8548EVTAVHD557 von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | MPC8548ECVTAQGD | MPC8548EVTAVHD557 |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Obsolete | NRND |
| Core Processor | PowerPC e500 | — |
| Number of Cores | 1 | — |
| Core Architecture | 32-Bit Power Architecture | — |
| Core Frequency | 1.0 GHz | 1.5 GHz |
| Co-Processors / DSP | Signal Processing Engine (SPE); Security Engine (SEC) | — |
| Memory Controllers | DDR, DDR2, SDRAM | — |
| Graphics Acceleration | No | — |
| Ethernet | Gigabit Ethernet (multiple MACs, SGMII) | — |
| PCI Interfaces | PCI, PCI-X, PCI Express | — |
| Serial RapidIO (SRIO) | Yes | — |
| Process Technology | 0.09 um CMOS | — |
| Versorgungsspannung | 1.8 V / 2.5 V / 3.3 V | 1.0 V core / 1.5 V DDR / 1.8 V / 2.5 V / 3.3 V I/O |
| Gehäuse | 783-pin FCBGA (29x29 mm) | 783-ball FCBGA, 29x29 mm |
| Betriebstemperatur | -40 C to +105 C | 0 C to +105 C (extended) |
| Silicon Revision | R3.0 | — |
| Series | MPC85xx (PowerQUICC III) | — |
| Montageart | Surface Mount | — |
| RoHS-Status | Compliant | Compliant (lead-free FCBGA) |
| Family | — | PowerQUICC III (MPC85xx) |
| Core | — | Power Architecture e500, 32-bit |
| Instruction Set | — | Power Architecture Book E + signal-processing engine |
| FPU | — | Double-precision hardware FPU |
| L1 Cache | — | 32 KB instruction + 32 KB data |
| L2 Cache | — | [DATA_NEEDED: L2 cache size] |
| Security Engine | — | SEC 2.0 (IPsec, SSL/TLS, 3DES, AES, SHA, RSA, ECC) |
| Gigabit Ethernet | — | 3x 10/100/1000 enhanced GETH with SGMII / RGMII / RTBI |
| PCI Express | — | 2x PCIe interfaces (x1/x2/x4 capable) |
| Serial RapidIO | — | 2x SRIO ports (1x/4x lane) |
| DDR Memory Controller | — | 2x 64-bit DDR2 with ECC, up to 533 MHz |
| PCI / PCI-X | — | 2x 64-bit PCI / PCI-X controllers |
| Local Bus | — | 8-bit / 16-bit / 32-bit Local Bus + GPIO |
| Serial I/O | — | 4x I2C, 2x UART, DUART, SPI |
| Process Node | — | 90 nm CMOS |