P5010NXN1QMB557 vs P5010NXE1QMB Vergleich
Detaillierter Direktvergleich von P5010NXN1QMB557 von NXP Semiconductors und P5010NXE1QMB von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
P5010NXN1QMB557 - QorIQ P5 2GHz 64-Bit MPU | NXP 1295-FCPBGA
P5010NXN1QMB557 ✓ AktivSpezifikationsvergleich
| Parameter | P5010NXN1QMB557 | P5010NXE1QMB |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $129,60 | $195,50 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | QorIQ P5 | — |
| Core Architecture | PowerPC e5500, 64-bit | — |
| Number of Cores | 1 | — |
| Maximum Core Frequency | 2.0 GHz | — |
| External Data Bus Width | 64-bit | — |
| Address Bus Width | 16-bit (per Microchip USA listing) | — |
| Gehäuse | 1295-ball FCPBGA (37.5 x 37.5 mm) | 1295-FCPBGA, 37.5x37.5 mm, 1.00 mm pitch |
| Ball Pitch | 1.00 mm | — |
| JESD-30 Package Code | S-PBGA-B1295 | — |
| Process Technology | CMOS | — |
| Integrated Cache | Yes (L1 + L2) | — |
| Low-Power Mode Support | Yes | — |
| RoHS-Status | Compliant | Compliant |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +105C (extended, NX suffix) |
| Montageart | Surface Mount (BGA) | — |
| Architecture | — | Power Architecture e5500, 64-bit |
| Core Count | — | 1 (single core) |
| CPU Frequency (nominal) | — | 1.6 GHz |
| CPU Frequency (turbo) | — | 2.0 GHz |
| Family | — | QorIQ P5 |
| L2 Cache | — | 512 KB per core |
| Memory Controller | — | DDR3 / DDR3L with ECC up to 1.33 GT/s |
| Ethernet | — | Gigabit Ethernet (multiple MACs) |
| PCIe | — | PCI Express Gen2 (multiple lanes) |
| Serial RapidIO | — | 2x SRIO ports |
| Security Engine | — | SEC 4.x (E1 suffix enabled) |
| HW Acceleration | — | Pattern matching engine for packet classification |
| Core Voltage | — | 1.1 V |
| Process | — | 45 nm CMOS |