P5010NXN1QMB557 vs P5010NXE1QMB Comparação
Comparação detalhada lado a lado de P5010NXN1QMB557 por NXP Semiconductors e P5010NXE1QMB por NXP Semiconductors. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
NXP Semiconductors
P5010NXN1QMB557 - QorIQ P5 2GHz 64-Bit MPU | NXP 1295-FCPBGA
P5010NXN1QMB557 ✓ AtivoComparação de especificações
| Parâmetro | P5010NXN1QMB557 | P5010NXE1QMB |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoria | Microcontrollers | Microcontrollers |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $129,60 | $195,50 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | QorIQ P5 | — |
| Core Architecture | PowerPC e5500, 64-bit | — |
| Number of Cores | 1 | — |
| Maximum Core Frequency | 2.0 GHz | — |
| External Data Bus Width | 64-bit | — |
| Address Bus Width | 16-bit (per Microchip USA listing) | — |
| Encapsulamento | 1295-ball FCPBGA (37.5 x 37.5 mm) | 1295-FCPBGA, 37.5x37.5 mm, 1.00 mm pitch |
| Ball Pitch | 1.00 mm | — |
| JESD-30 Package Code | S-PBGA-B1295 | — |
| Process Technology | CMOS | — |
| Integrated Cache | Yes (L1 + L2) | — |
| Low-Power Mode Support | Yes | — |
| Status RoHS | Compliant | Compliant |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | -40C to +105C (extended, NX suffix) |
| Tipo de montagem | Surface Mount (BGA) | — |
| Architecture | — | Power Architecture e5500, 64-bit |
| Core Count | — | 1 (single core) |
| CPU Frequency (nominal) | — | 1.6 GHz |
| CPU Frequency (turbo) | — | 2.0 GHz |
| Family | — | QorIQ P5 |
| L2 Cache | — | 512 KB per core |
| Memory Controller | — | DDR3 / DDR3L with ECC up to 1.33 GT/s |
| Ethernet | — | Gigabit Ethernet (multiple MACs) |
| PCIe | — | PCI Express Gen2 (multiple lanes) |
| Serial RapidIO | — | 2x SRIO ports |
| Security Engine | — | SEC 4.x (E1 suffix enabled) |
| HW Acceleration | — | Pattern matching engine for packet classification |
| Core Voltage | — | 1.1 V |
| Process | — | 45 nm CMOS |